The present invention relates to a nonvolatile, integrated-circuit memory such as an electrically-erasable, electrically-programmable read-only-memory (EEPROM), and more particularly to an EEPROM memory cell that is programmed by hot-carrier injection and is erased by Fowler-Nordheim tunneling, and to a method of fabricating such a device.
EEPROMs use field-effect transistors with floating-gate structures which are programmed and erased by storing and removing charges from the electrically isolated floating gates. The digital information stored in EEPROMs is read by differentiating between the source-drain impedance presented by a charged (high Vt) floating gate and an uncharged (low Vt) floating gate. Depending on construction, EEPROMs may be erased cell-by-cell, segment-by-segment, all cells at one time (flash-erase mode), or combinations of the foregoing.
In general, EEPROMs use one of two charge transfer mechanisms for programming operations--either Fowler-Nordheim tunneling or hot-carrier injection. Fowler-Nordheim tunneling is generally used for erase operations. EEPROMs using hot-carrier injection programming typically employ FAMOS (Floating-gate, Avalanche-injection MOS) structures, although hot-carrier injection results from channel-hot electrons as well as avalanche breakdown (assuming NMOS).
Each of the two charge transfer mechanisms has advantages and disadvantages in comparison to the other mechanism. Programming an EEPROM memory cell by hot-carrier injection requires lower voltage than the voltage required for Fowler-Nordheim tunneling. On the other hand, the higher voltage required for Fowler-Nordheim tunneling can be generated on-chip because of the relatively small tunneling-current required. In many cases, an additional power supply is required to meet the higher programming-current requirement for hot-carrier injection. Moreover, floating-gate erasure using hot-carrier injection of holes may cause damage to the oxide insulator layer, leading to cell degradation and failure. Use of Fowler-Nordheim tunneling for erasing causes significantly less damage to the tunnel-window oxide and is, therefore, preferable for cell durability and reliability.
EEPROMs using hot-carrier injection for programming and using Fowler-Nordheim tunneling for erasure have been described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM," S. Mukherjee, et al., IEDM 1985 (p. 616-619), (b) "An In-System Reprogrammable 256K CMOS Flash Memory", V. N. Kynett, et al., ISSCC 1988 (p. 132-133), and (c) "A 128K Flash EEPROM using double polysilicon Technology", George Samachisa et al., ISSCC 1987 (p. 87-88). These EEPROMs employ a conventional architecture in which the drains of two memory cells share one contact. Gate oxide thickness is a trade-off between adequate tunneling current for erase in a reasonable time, and the impact on yields/reliability from processing defects. That is, thick gate oxide improves process yields/reliability, but reduces tunnel current, which leads to long erase times. Moreover, the junction breakdown voltage is lowered with thin gate oxide, so that, during erase, excessive junction leakage (and the unwanted generation of hot carriers) can occur before the onset of adequate Fowler-Nordheim tunnel erase current. (See, References (b) and (c).) Thus, these EEPROMs are erased, in part, by hot holes because of low field plate breakdown voltage of the source-channel junction of the floating-gate transistor.
The approach in Reference (c) uses a channel oxide of about 200 Angstroms, and uses channel-hot-electron injection for programming, and Fowler-Nordheim tunneling for erasure from the same junction. It has two disadvantages: (i) the junction optimization requirements for erasing/programming are incompatible, and cannot be met by the same junction; and (ii) a gate oxide thickness of 200 Angstroms does not allow adequate Fowler-Nordheim tunneling current for reasonable erase times with conventional 12.5 V EEPROM power supplies. As a result, junction-breakdown-assisted erase can occur, leading to excessive substrate current during erase.
Thus, EEPROMs, heretofore, have not combined hot-carrier injection programming with strictly Fowler-Nordheim tunnel erasing. One problem has been that the higher voltages required by Fowler-Nordheim tunnel erasing leads to source-channel junction field-plate breakdown, and the unwanted generation of hot carriers. Related application Ser. No. 07/219,529, now abandoned, discloses a memory cell configuration in which a Fowler-Nordheim tunnel window is located on a side of the source opposite the channel, and the junction under the tunnel window terminates under a relatively thick oxide, thereby improving source-junction field-plate breakdown.
Accordingly, a need exists for an EEPROM that is programmed using only hot-carrier injection, and is erased using only Fowler-Nordheim tunneling, in a contact-free array configuration. Such an EEPROM would take advantage of the relatively low voltage required for hot-carrier injection programming while avoiding channel insulator damage due to hot-carrier erasure, thereby improving the durability and reliability of the memory cell. In addition, the reduced number of array contacts would provide improved process yields and improved reliability. In general, a satisfactory memory cell of this type would provide careful control over the channel and junction profile to achieve optimum efficiency for hot-carrier-injection programming.
Related application Ser. No. 07/458,936, now U.S. Pat. No. 5,010,028 discloses a structure and method for a buried-bitline-type of EEPROM that is programmed by hot-carrier injection and that is erased by Fowler-Nordheim tunnelling. The structure and method of this invention provide alternatives to the structure and method of that invention. In particular, the floating-gate structure of this invention has three sections, rather than the two sections shown in the aforementioned related application. The third section, or tunnel-window section, provides protection for the Fowler-Nordheim tunnel-window during latter stages of the construction process.